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PARAMETER
SYMBOL
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
SDA data set-up time
SCL clock low period
SCL clock high period
t SU:DAT
t LOW
t HIGH
100
0.5
0.26
ns
μs
μs
SDA, SCL fall time
SDA, SCL rise time
SDA, SCL input suppression filter period
t f
t r
t SP
(Note 6, Note 7)
(Note 7)
50
120
120
ns
ns
ns
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Subject to thermal dissipation characteristics of the device.
Guaranteed by design, and not production tested.
Minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if either SDA or SCL is held low for t timeout .
Disable bus timeout via the power control register, 0x02[6].
t VD:ACK = SCL low to SDA (out) low acknowledge time.
t VD:DAT = minimum SDA output data-valid time following SCL low transition.
A master device must provide an SDA hold time of at least 300ns to ensure an SCL low state.
The maximum SDA and SCL rise and fall time specifications are influenced by the speed of operation required. The original Philips Corp. I 2 C
specification allows slower values, but because the MSL3167/8 interface is designed to operate at speeds exceeding the original specification,
these timing values have tightened up. Maximum bus speed is also influenced by bus capacitance. Lay out bus traces to minimize capacitance when
high-speed operation is required.
MSL3167/8 include input filters on SDA and SCL inputs that suppress noise less than 50ns.
Block Diagram
8
Atmel LED Drivers-MSL3167/MSL3168
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